The present invention relates to a semiconductor device in which a complementary MOS circuit is formed on a semiconductor substrate.
With the recent development of MOS-LSI techniques, CMOS-LSIs have attracted much attention because of their low power consumption so that they will be widely used in various fields. However, they have some problems which may be summarized as follows:
(1) Since the value of the parasitic junction capacitance between a substrate, source and drain is high, the high speed or faster operation cannot be attained.
(2) Since a PNPN switch between the substrate and the source is turned on, the latch-up problem results.
(3) Even when the dimensions of an element are decreased, the high speed operation cannot be attained.
(4) Adverse effects due to variations in external power supply cannot be avoided.